Vhdl Program For 8 Bit Up Down Counter Two
8-bit Art Maker
Library ieee;use ieee.stdlogic1164.all;use ieee.stdlogicsigned.all;entity counter isport(CLK, CLR: in stdlogic;output: inout stdlogicvector(3 downto 0));end counter;architecture archi of counter issignal tmp: stdlogicvector(3 downto 0);beginprocess (CLK, CLR)variable i: integer:=0;beginif (CLR='1') thentmp. Needs to operate off one clock edgeBecause your counter port has clk in it, we can assume you want the counter to count synchronous to the clock.You're operating off of both clock edges elsif (clk = '1') thenshould be something like elsif clk'event and clk = '1' thenor elsif risingedge(clk) thenThese examples use the rising edge of clk. You can't synthesize something that uses both clock edges under the IEEE-1076.6 IEEE Standard for VHDL RegisterTransfer Level (RTL) Synthesis. It's not a recognized clocking method. Making a modulo 10 counterUnder the assumption you want the counter to go from 0 to 9 and rollover this for i in 0 to 6 looptmp '0'); # equivalent to '0000'elsetmp.
How could this VHDL counter and its test bench be improved? I am interested in anything you see that could be done better, but especially in the test bench: Is wait for 10 ns better or worse than any other time delay? The test is very minimal. Dna activation wikipedia. Should it do more?